In semiconductor integrated circuit manufacturing, it is conventional to test the integrated circuits (“ICs”) during manufacturing and prior to shipment to ensure proper operation and related characteristics. Wafer testing is a well-known testing technique commonly used in production testing of wafer-based semiconductor ICs (or dice), wherein a temporary electrical current is established between, for example, automatic test equipment (ATE) and each IC (or die) of the wafer to demonstrate proper performance of the ICs. Exemplary components used in wafer testing include an ATE test board, which is a multilayer printed circuit board that is connected to the ATE, and that transfers the test signals back and forth between the ATE and a probe card.
An exemplary probe card includes a printed circuit board (PCB) having contacts in electrical communication with several hundred probe needles positioned to establish electrical contact with a series of connection terminals (or die contacts) on the IC wafer. Certain known probe cards further include a substrate or so-called space transformer which electrically connects the probes to the printed circuit board. The space transformer may include, for example, a multi-layer ceramic substrate or a multi-layer organic substrate. It is known to mount each of the plurality of flexible probes to a mounting surface of the space transformer. Typically, the probes are mounted to electrically conductive (e.g., metallic) bonding pads formed on the substrate through conventional plating or etching techniques well known to those of ordinary skill in the art of semiconductor fabrication. In certain alternatively configured probe cards, it is known to mount the probes within a probe head assembly which positions ends of the probes in electrical communication with contacts on the space transformer surface.
One difficulty in the fabrication of probe cards is that the mounting surface of the space transformer substrate is desirably maintained within a tight flatness tolerance, such that undesirable variation in the positions of the probe tips, which connect with the IC connection terminals, is minimized. Tight positional tolerances of all the probe tips within the probe assembly are crucial for establishing and maintaining identical contacting conditions between the individual probe tips and the terminals of the tested chips. Positional tolerances affect both the position of the probe tips relative to the corresponding terminals and the force required to establish a satisfactory electrical connection between the probes and the IC connection terminals. In order to tightly control positional tolerances of the probe tips, it is desirable that the mounting surface of the plurality of probes be as nearly planar as practicable.
In particular, one common approach for mounting probes to a substrate includes a step of using plating techniques to form a post structure on the substrate followed by a step of tab bonding each probe to a post. It is difficult to maintain the top of each of the plated posts on a common plane. Furthermore, it is difficult to maintain proper alignment of the probes as the probes are mounted to the posts.
A further disadvantage of mounting probes directly to the space transformer substrate is that the substrate tends to be a relatively expensive item, and if errors are made during the process of mounting the probes to the substrate such that the substrate is rendered useless, the cost of such errors is significant.
Thus, it would be desirable to provide a more easily manufactured and more cost-effective probe card providing probe elements having tips positioned within tight tolerances.